1. Field of the Invention
This invention relates to a semiconductor device and relates in particular to a semiconductor memory device. More particularly, this invention relates to a semiconductor memory device containing a highly integrated and highly reliable memory utilizing an amplifying memory cell.
2. Description of Related Art
The widely used dynamic random access memory (DRAM) is a single transistor cell utilized as a memory cell and consisting of a single transistor and a single capacitor. However in recent years, as MOS transistors (MOSFET: Metal Oxide Semiconductor Field Effect Transistor) in semiconductor devices become more highly integrated and more miniaturized, the breakdown voltage becomes lower and the operating voltage has also become lower to achieve lower electrical power consumption also becomes lower. In addition, in a DRAM utilizing a single transistor cell, the memory cell itself has no amplifying action so that the read out signal level from the memory cell is small and operation tends to be unstable because of effects from all types of noise.
So, a memory cell utilizing three transistors (hereafter three-transistor cell) and previously used prior to the single transistor cell is again attracting attention as a memory cell capable of delivering a large read-out signal level by an amplifying action. This three-transistor cell is described for instance in the IEEE International Solid-State Conference, DIGEST OF TECHNICAL PAPERS, pp. 10-11, 1972).
This memory cell for example as shown in FIG. 2, is comprised of a read-out NMOS transistor QR, a write NMOS transistor QW, and also a charge holding NMOS transistor QN. The gates of the transistors QR and QW are connected to the word line WL, and the source is connected to the data line DL. The gate of the transistor QN is connected to the drain of the transistor QW, and the source of the transistor QN is connected to the source line SL. The transistor QN, QR drains are also connected. Here, the threshold voltage VTW of the transistor QW is set higher than the threshold voltage VTR of transistor QR, and the data line voltage amplitude is equal to the supply voltage amplitude VDL. In a memory cell configured this way, the word line voltage for the write operation must be a high write voltage VW higher than the threshold voltage VTW, and this value is generally set higher than the supply voltage VDL. Also, the word line voltage for the read operation must be a read voltage VR higher than the threshold voltage VTR, and lower than the threshold voltage VTW and this value is generally set between the supply voltage level VDL and ground potential. Further, the standby state (non-select state) of the word line voltage must be lower than the word line voltage VTR and is set for example at ground potential VSS.
A device having an amplifying memory cell comprised of one capacitor and two transistors (hereafter called capacitive coupling 2-transistor cell) is described in IEEE ELECTRONICS LETTERS 13th May, 1999 Vol. 35 No. 10, pp. 848-850).
This memory cell as shown in FIG. 3, is comprised of a read NMOS transistor QR, a write transistor QW, and also a coupling capacitor Cc for controlling the voltage of the memory cell node N. The transistors QR and QW are in a stacked configuration so this device is characterized by a small surface area. A transistor utilizing the tunnel effect is used as transistor QW so the leak current is small. These components are connected as follows. One end of the capacitor Cc and the gate of transistor QW are connected to the word line WL, and the source of transistor QW is connected to bit line BL. The other end of the capacitor Cc and the drain of the transistor QW are connected to the gate of the transistor QR, and the memory cell node N thus formed. The source of the transistor QR is grounded, and the drain connected to the sense line SL. The word line voltage VW for writing and the word line voltage VR for reading are respectively set in this kind of cell, as described for the three-transistor cell shown in FIG. 2.
However, in the standby state (non-select state), the voltage potential VN (H) for the standby state of the memory cell node N written at the supply voltage level VDL, must be a word line voltage at a lower voltage potential than VTR, for instance the standby voltage −VB must be set lower than the ground voltage VSS. Therefore, in the three-transistor cell and the capacitive coupling type 2-transistor cell as described above, the read and write operation is controlled by a read voltage VR and write voltage VW applied to one word line.